1. Technical Field
This invention relates to the field of testing semiconductor devices. More specifically, the invention relates to a method for testing and guaranteeing that skew between two signals meets predetermined criteria.
2. Background Art
Computer chips have become extremely complex: Millions of logic devices can be made to fit on one chip. Because of this complexity, it is essential that these chips be tested. Prior to use, the computer chip is placed into a tester to ensure that signals meet timing requirements. One important criterion for testing signals is skew. Skew is the difference in arrival time, at a particular location, between two signals. For some signals, it is desired that there be very little skew. Generally, limits are placed on the skew between two or more signals so that the signals arrive at a specific location at about the same time. If the signals do not meet skew requirements, it is possible for incorrect data to be read or written.
Skew is particularly important for memory devices. For memory, the data must be valid for a particular time period before the memory controller or other device reads the data. If this is not the case, incorrect data may be read.
With Synchronous Dynamic Random Access Memories (SDRAMs), data output supplied by the DRAM during read cycles is available on the data pins a certain time after a rising clock edge provided to the SDRAM. This time period is known as tAC, or access time from CLK, and is typically in the 5-6 nanosecond (ns) range. Such a period is shown in FIG. 7, which shows a typical SDRAM cycle. In this cycle, the data (which are labeled DQ) must be available on the data pins a certain time after the rising clock edge shown in the figure. The clock has a 10 ns period, beginning at 25 ns, and a rising clock edge at 25 ns. Individual data signals from the data are transitioning in the hashed region. Ideally, each data signal would transition at the same time, but inaccuracies cause some of the data signals to transition at different times. Each data signal must complete its transition before the memory controller or other device reads the data.
The tAC timing parameter is a maximum specification (illustrated as tAC(max) in FIG. 7) and must be guaranteed by testing each device. This is accomplished on standard memory testers by xe2x80x9cstrobingxe2x80x9d the DQ outputs with a tester xe2x80x9cedge strobexe2x80x9d. The edge strobe is strobed 5-6 ns after a certain rising clock edge. The edge strobe is also shown in FIG. 7. If the data captured by the edge strobe is valid (and this is repeated for all column address locations), then the device is verified to pass the tAC(max) specification. Due to tester inaccuracies of strobing the data exactly (for instance) 5 ns after the rising clock edge, a tester xe2x80x9cguardbandxe2x80x9d must be accounted for when taking the tAC(max) measurement. This guardband is specified by the tester vendor and is typically in the 200-350 picosecond (ps) range. Because of the edge strobe placement inaccuracy, the edge strobe may be generated anywhere in the range of 4.7 to 5.3 ns. Therefore, in order to guarantee that a device under test meets the tAC(max) specification, the tester xe2x80x9cedge strobexe2x80x9d is set at 4.7-4.8 ns to guarantee a 5 ns tAC(max). This xe2x80x9cguardbandingxe2x80x9d requirement often results in over testing the device and results in unnecessary yield loss.
Currently, Double Data Rate (DDR) DRAMs have been introduced. With the introduction of DDR SDRAMs, the DRAM read cycles have been enhanced to include the addition of a data strobe. The purpose of the data strobe is to coincidently drive a source synchronous signal from the DRAM with the valid read data. The data strobe essentially informs the reading devices as to when the data is valid. The data strobe and the data are sourced from the same chip and the DQS and data signals travel together on a set of parallel wires that should be laid out identically. This minimizes the skew that would otherwise occur between the system clock and the data driven from the DRAM. When the data strobe arrives at the memory controller, it is delayed by some amount and then used to latch the data into the memory controller.
The data strobe (DQS) is an edge driven strobe that transitions from low to high coincident with the first data driven out of the RAM on the read cycle; it then transitions from high to low with the second data delivered from the RAM. The data strobe continues to transition low to high and high to low with all valid data driven consecutively from the RAM.
The purpose of the data strobe is to provide a latching signal from the RAM to the memory controller to indicate that valid data is on the data bus for the memory controller to capture or latch. A typical DDR DRAM cycle is shown in FIG. 8. The data strobe (DQS) is nominally aligned with the clock (CLK). The data strobe (DQS) is also nominally aligned to be valid at the same instant that data (DQ) is valid on the bus. However, due to p- and n-channel processing skews, data pattern dependent noise, and physical layout mismatches of the chip, there can exist a skew between valid data strobe and valid data. This skew may be positive. In this case, the data strobe arrives before the data. The maximum tolerable skew in this instance is referred to as tDQSQ(max). This skew may also be negative. In this case, the data strobe arrives after the data. The maximum tolerable skew in the negative skew case is referred to as tDQSQ(min). In both cases, the receiving device must know how large this skew is so that it can properly delay the data strobe an appropriate amount to position it in the middle of the valid data window to properly latch the data. This is shown in FIG. 8. Also shown in FIG. 8 is the nominal tDQSQ, which is indicated as tDQSQ(nom) and which means that the data strobe arrives exactly at the same time that the data becomes valid.
With the current installed base of manufacturing testers, it becomes hard to measure the data strobe-to-data skew. The data strobe-to-data skew is typically in the range of 500 to 600 ps and is very difficult if not impossible to measure directly on a tester using a single xe2x80x9cedge strobexe2x80x9d in a similar manner to the method used to measure tAC(max). Because the data strobe generated by the RAM is not fixed with respect to the input clock, and because the data is not fixed with respect to the clock or the data strobe, an xe2x80x9cedge strobexe2x80x9d measurement is ineffective in measuring the skew between data strobe and the data signals.
There are two reasons for this. First, the edge strobes are generally referenced from the clock. For instance, in FIG. 8, edges 1 and 2 are referenced from the falling edge of the clock that occurs at 22.5 ns. The first edge strobe (edge strobe 1) is made to xe2x80x9cexactlyxe2x80x9d strobe on the clock""s falling edge, while the second edge strobe should strobe at the tDQSQ(min) time. However, although the data strobe is shown synchronized to the clock, the data strobe generally lags the system input clock. DDR DRAMS contain a digital locked loop (DLL) on the chip that aligns both the data strobe and data to the system clock during read cycles; however, the DLL is not perfectly accurate. It has resolution errors, and will be off by some number of picoseconds. This means that the edge strobes, which are referenced to the clock, are trying to track the data strobe and data signals, which are only marginally referenced to the clock.
Secondly, the important signals being measured are the data skew. This skew ranges from about 500 to 600 ps. Ideally, one edge strobe on the tester would be exactly aligned with the rising or falling edge of the data strobe, and another edge strobe would be exactly aligned with a location or time at which the data becomes valid. This is shown in FIG. 8, where at time 1 the first edge strobe aligns with the falling edge of the data strobe and at time 2 the second data strobe aligns with the point at which the data becomes valid. If the absolute time difference between the two edge strobes is less than tDQSQ(min), then the memory device meets the criteria for skew. If the time difference is greater than tDQSQ(max), then the memory device does not meet the criteria for skew. Because there are errors in the placement of the edge strobes, it is very hard to measure 500-600 ps without over- or under-testing the actual skew. For example, in FIG. 8, the second edge strobe might (due to placement error) actually rise at time 3 instead of time 2. This would cause edge strobe 2 to strobe invalid data, which would indicate an error for a cycle that is within specifications. Commonly, edge strobes can have errors in edge strobe placement of 300 or more picoseconds. Thus, it is impractical to try to measure a data strobe-to-data skew of 500 ps with two edge strobes fixed relative to the system input clock, with each strobe having placement accuracy error up to 300 ps, and where the skew has cycle-to-cycle variability.
It is possible for the testers to be improved upon to reduce the edge strobe error. However, this results in significant cost and renders current tester useless. Other ways of ensuring skew is by guaranteeing by design or by characterization or by using a xe2x80x9csample and averagexe2x80x9d technique. However, these are only estimates or theoretical assumptions and actual devices may fail outside the statistical limits.
For these reasons, what is needed a method to determine if skew between signals is within specifications, without creating new testing devices or creating potentially invalid assumptions.
To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.